The present disclosure herein relates to semiconductor devices and, more particularly, to three-dimensional semiconductor devices.
Semiconductor devices may be attractive to the electronics industry because of their small size, multi-function capabilities, and/or low fabrication costs. For example, high-performance semiconductor devices and/or low-cost semiconductor devices have experienced increased demand with the development of the electronics industry. In order to address these demands, semiconductor devices have become more highly-integrated. In particular, the integration density of semiconductor memory devices has increased to store more logic data.
A planar area occupied by a unit memory cell may directly affect the integration density of two-dimensional semiconductor memory devices. In other words, the integration density of the two-dimensional semiconductor memory devices may be influenced by a minimum feature size that relates to a process technology for forming fine patterns. However, there may be limitations in improving the process technology for forming the fine patterns. Additionally, high-cost equipment or apparatuses may be required to form the fine patterns. Thus, the costs of fabricating highly-integrated semiconductor memory devices may be relatively high.
Three-dimensional semiconductor memory devices have been proposed to address some of the above limitations. The three-dimensional semiconductor memory devices include a plurality of memory cells that are three-dimensionally arrayed. However, in fabrication of the three-dimensional semiconductor memory devices, various problems may occur due to structural configurations thereof. As a result, reliability and/or electrical characteristics of the three-dimensional semiconductor memory devices may be relatively weak.